A programmable logic device (PLD) is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., flash memory, as in some CPLDs), or in any other type of memory cell.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, commonly called flash memory. An example of a non-volatile memory is a read-only memory (ROM) (e.g. a programmable ROM (PROM), an erasable PROM (EPROM), or an electrically erasable PROM (EEPROM)) either external to or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of the configuration logic blocks. At the end of this start-up phase, the PLD is now specialized to the user's design, and the PLD enters into a “user” mode as part of its normal operation.
However, there are several cases in which the data stored in the non-volatile memory required for a given task is mis-programmed, invalid, corrupted or otherwise incorrect. During a write cycle of the non-volatile memory, interrupts may occur that corrupt the programming of a valid bitstream. Retention failures of a non-volatile memory may also cause interim upset of locations over time. Configuration failures are often identified by either a failed cyclic redundancy check (CRC) or a missed preamble. If the bitstream has somehow become corrupted, the CRC failure will likely occur again and again. If there is an absence of the preamble, there will be no synchronization or “sync” word, which normally signifies the beginning of configuration data. Without the sync word, the FPGA will not report a CRC response, leading to a common misconception that the FPGA is defective or that the FPGA may require more configuration clocks to be sent.
Most applications that require read or write access to non-volatile memory assume that the data in the non-volatile memory is valid and do not provide any method of verifying the data before using it. In many cases, the actions to be performed involving the non-volatile memory are critical to the functionality of the main device, such as an FPGA, of a system. For example, during the configuration of an FPGA, data from a separate non-volatile memory is delivered into the FPGA's configuration memory. If the configuration was successful, the FPGA will become operational. However, there is no way of determining, before attempting to configure a conventional device having programmable logic, if the data in the non-volatile memory is valid. The use of invalid data may cause an entire operation of the conventional device to fail. For example, it was simply assumed the data will be valid, and no solution is provided if invalid data is used in the application. While conventional methods accommodate the use of invalid data, such use of a device having invalid data is undesirable. Alternatively, a third device may be used to recover the system in the event of a failed configuration. However, the user of a third device results in an inefficient use of resources.
Accordingly, there is a need for an improved method of and system for verifying configuration data loaded into a device having programmable logic.